The most obvious benefit of stacking is a smaller footprint for the CIS and processor combo. However, stacking still faces some specific challenges starting with higher NRE costs and limited technology processes available to select customers. The added complexities during characterization, qualification, and production will require customers to carefully consider design choices. The presentation will describe how Forza is addressing the challenges by developing custom stacking flows involving intelligent design choices and good product engineering.
“Forza Silicon has been working on stacked CMOS image sensors since 2011 as part of the DARPA SCENICC Program and other DoD initiatives,” said Mansoorian. “Stacked sensor design is something we believe will dominate advances in the CIS marketplace for the next 3 to 5 years, and Forza will continue to improve image sensor design processes to help our customers take advantage of enhanced technology options.”
