Altasens' patent application US20120267511 "Image sensor with hybrid heterostructure" by Lester Kozlowski has few interesting claims:
First, a stacked sensor structure is proposed:
The pixel array uses "optimized" pmos transistors. An example pixel capable of GS, S&H and CDS is shown on Fig. 6:
The main advantages of the stacked structure are (1) very good global shutter efficiency and (2) lower noise due to a special pmos transistor "optimization":
"FIGS. 7 and 8 [not shown here] compare the read noise achievable with optimized PMOS technology vs. standard CMOS technology wherein the source follower is formed in NMOS having flicker noise lower than readily achieved in common foundry processes, i.e., very good compared to what is readily available. Even so, the PMOS global shutter can yield a read noise of 1 e− (or holes) at a sense capacitance of 5 fF. The NMOS global shutter circuit instead has read noise of 3.5 e− at 5.5 fF. More importantly for long term development, the PMOS solution goes well below 1 e−0 as the sense capacitance is reduced while the NMOS solution plateaus well above 2 e−."
First, a stacked sensor structure is proposed:
The pixel array uses "optimized" pmos transistors. An example pixel capable of GS, S&H and CDS is shown on Fig. 6:
The main advantages of the stacked structure are (1) very good global shutter efficiency and (2) lower noise due to a special pmos transistor "optimization":
"FIGS. 7 and 8 [not shown here] compare the read noise achievable with optimized PMOS technology vs. standard CMOS technology wherein the source follower is formed in NMOS having flicker noise lower than readily achieved in common foundry processes, i.e., very good compared to what is readily available. Even so, the PMOS global shutter can yield a read noise of 1 e− (or holes) at a sense capacitance of 5 fF. The NMOS global shutter circuit instead has read noise of 3.5 e− at 5.5 fF. More importantly for long term development, the PMOS solution goes well below 1 e−0 as the sense capacitance is reduced while the NMOS solution plateaus well above 2 e−."
