Business Wire: Sony increases its production capacity for stacked CMOS sensors in the fiscal year ending March 31, 2016 ("FY15"). Sony Semiconductor also plans to reorganize and optimize its production sites as it accelerates the shifting of resources to the image sensor business.
This investment is intended primarily to augment production facilities used in the mastering and layering processes for stacked CMOS image sensors, specifically at Sony Semiconductor's Nagasaki Technology Center ("Nagasaki TEC"), Yamagata Technology Center ("Yamagata TEC"), and Kumamoto Technology Center ("Kumamoto TEC"). The mastering process refers to the manufacture of photodiodes and wiring processes for stacked CMOS image sensors. The layering process refers to the layering of semiconductor chips containing back-illuminated structure pixels on top of semiconductor chips containing the circuit for signal processing.
With this investment, Sony plans to increase total production capacity for image sensors from its current level of approximately 60,000 300mm-equivalent wafers per month to approximately 80,000 300mm wafers per month by the end of June 2016. Previously, as a mid to long range target, Sony had aimed to raise its total production capacity for image sensors to approximately 75,000 wafers per month. To facilitate this increased production, Sony has continued to augment production facilities at each site, and it established Yamagata TEC in March 2014. Through this investment, Sony will exceed its previous target ahead of schedule.
The total investment amount is projected to be approximately 105 billion yen, comprising approximately 78 billion yen of investments in Nagasaki TEC, approximately 10 billion yen of investments in Yamagata TEC and approximately 17 billion yen of investments in Kumamoto TEC.
This investment is intended primarily to augment production facilities used in the mastering and layering processes for stacked CMOS image sensors, specifically at Sony Semiconductor's Nagasaki Technology Center ("Nagasaki TEC"), Yamagata Technology Center ("Yamagata TEC"), and Kumamoto Technology Center ("Kumamoto TEC"). The mastering process refers to the manufacture of photodiodes and wiring processes for stacked CMOS image sensors. The layering process refers to the layering of semiconductor chips containing back-illuminated structure pixels on top of semiconductor chips containing the circuit for signal processing.
With this investment, Sony plans to increase total production capacity for image sensors from its current level of approximately 60,000 300mm-equivalent wafers per month to approximately 80,000 300mm wafers per month by the end of June 2016. Previously, as a mid to long range target, Sony had aimed to raise its total production capacity for image sensors to approximately 75,000 wafers per month. To facilitate this increased production, Sony has continued to augment production facilities at each site, and it established Yamagata TEC in March 2014. Through this investment, Sony will exceed its previous target ahead of schedule.
The total investment amount is projected to be approximately 105 billion yen, comprising approximately 78 billion yen of investments in Nagasaki TEC, approximately 10 billion yen of investments in Yamagata TEC and approximately 17 billion yen of investments in Kumamoto TEC.
