Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling Analog-to-Digital Conversion
Authors: Ignjatovic, Z. (Electr. & Comput. Eng. Dept., Univ. of Rochester, Rochester, NY, USA), Maricic, D. ; Bocko, M.F.
ABSTRACT
"We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V."
Second, University of Rochester published Danijel Maričić PhD Thesis describing the techology in even more details: "Image Sensors Employing Oversampling Sigma-Delta Analog-to-Digital Conversion with High Dynamic Range and Low Power".
The 5T sigma-delta pixel uses both pmos and nmos transistors and 3T-like process (no PD transfer gate):
"Every frame scan generates one-bit per-pixel and the readout is repeated OSR times. The image is reconstructed by a digital decimation circuit synchronized with the readout. The comparator is designed for a sampling rate of #rows*max(OSR)*fps = 128*256*60 = 1.97MHz in order to achieve 60 full resolution frames per second following decimation."
The sensor parameters table shows the achieved performance level:
Few other sigma-delta sensor implementations are discussed in the Thesis, including the one having 3T pixel and digital integrator in the column readout (called "indirect feedback sensor):
This architecture is claimed to solve quite a lot of issues:
The manufactured prototype parameters look quite nice for 3T pixel with such a huge full well:
