The article explains why it's difficult to create a real dual-poly CCD process in advanced process nodes:
"However, by using size features less than 0.25 μm, dual-poly is no longer possible because process nodes starting at 180 nm and less uses a chemical mechanical polishing (CMP) process in the BEOL. CMP requires an absolutely flat surface for the layer deposition and structuring, so a second poly silicon layer is no longer possible. The key to a good CTE is a very narrow poly gap between the two gates. Such a narrow gap can be easily achieved by the use of a 45 nm (or less) process. However, because the non-recurring engineering and tooling costs (NRE) of such technology nodes are prohibitively high, they eliminate themselves as a candidate for a CCD implementation on CMOS. The ESPROS technology tackles this dilemma by a new designed manufacturing process. This new manufacturing process allows poly gaps of less than 100 nm, even in a standard 180 nm process environment."
"...a new mixed process from ESPROS Photonics that combines CMOS and CCD attributes addresses these limitations. The choice of a suitable substrate material contributes, among other things, to a fully depleted detector thickness of 50 μm. This results in a superior QE in the NIR region, maintaining >80% QE at λ = 850 nm and >50% QE at λ = 950 nm."
