Prof. Wang Qijie believes this to be the first time that a broad-spectrum, high photosensitive sensor has been developed using pure graphene. Prof Wang came up with an idea to create nanostructures on graphene which will “trap” light-generated electron particles for a much longer time, resulting in a much stronger electric signal.
The “trapped electrons” is the key to achieving high photoresponse in graphene, which makes it far more effective than the normal CMOS or CCD image sensors, said Asst Prof Wang. Essentially, the stronger the electric signals generated, the clearer and sharper the photos (the above description strongly points to photoconductive gain).
"The performance of our graphene sensor can be further improved, such as the response speed, through nanostructure engineering of graphene, and preliminary results already verified the feasibility of our concept," Asst Prof Wang added.
This research, costing about $200,000, is funded by the Nanyang Assistant Professorship start-up grant and supported partially by the Ministry of Education research grants. Development of this sensor took Asst Prof Wang a total of 2 years to complete. His team consisted of two research fellows, Dr Zhang Yongzhe and Dr Li Xiaohui, and four doctoral students Liu Tao, Meng Bo, Liang Guozhen and Hu Xiaonan, from EEE, NTU. Two undergraduate students were also involved.
The new graphene-based sensor is described in this month’s Nature Communications ("Broadband high photoresponse from pure monolayer graphene photodetector"). The next step is to work with industry collaborators to develop the graphene sensor into a commercial product.
From the paper's figures, it appears that the new sensor has a FET-like pixel structure and works best at cryogenic temperatures, such as 12K:
 |
| Fabrication process of the device. (a) A monolayer graphene was mechanically exfoliated onto a 285nm SiO2/Si substrate. (b) The graphene photodetector was processed into a FET structure. Two electrodes (that is, the source and the drain terminals) of Ti/Au (20 nm/80 nm) were fabricated on the graphene by photolithography and lift-off processes. The gate terminal was fabricated on the bottom of the Si substrate. (c) A thin nm-scale Ti sacrificial layer was deposited onto the graphene by electron-beam evaporation. (d) The Ti sacrificial layer was removed via wet etching, and then GQD array structure with various quantum dot (QD) sizes can be formed on the Si substrate depending on the thickness of the Ti layer. |
