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PR Newswire: Synopsys says its new DesignWare MIPI D-PHY is 50% lower in area and power compared to competitive solutions. The new IP is the first in the industry compliant to the MIPI D-PHY v1.2 spec (8 data lanes maximum instead of 4 lanes in v1.1), and delivers aggregated data throughput of up to 20 Gbps for high-resolution imaging (2.5 Gbps per lane, 8 lanes).
The new DesignWare MIPI D-PHY is available now in 16-nm FinFET processes, with availability in 28-nm processes scheduled for early 2015. VIP for MIPI D-PHY v1.2 is available now.
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By delivering an extremely small-area and low-power D-PHY to the fast-paced and competitive mobile market, Synopsys helps designers differentiate their SoCs in both silicon cost and battery life," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
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The DesignWare MIPI D-PHY offered low power consumption, high performance and configurability options that were critical to the success of our Myriad 2 Vision Processing Unit," said Sean Mitchell, SVP and COO at Movidius. As a side note, Myriad 2 has 12 lanes of 1.5 Gbps D-PHY in 28nm process, so I'm not sure it's relevant to this recent announcement.
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