The new platform, based on Tower's 0.16um CMOS shrink process, will allow easy re-use of existing customers' 0.18um circuit IP which will save them from investing in resources to redesign existing blocks, and increase the probability for first time success. The TS11IS offers improved pixel performance, smaller pixel pitch, higher resolution, improved sensitivity, and improved angular response. It allows up to 50% reduction of pixel size, mainly for high-end global shutter pixels.
The platform includes a new local interconnect layer to allow denser metallization routing in pixels while maintaining good QE. It also includes tighter design rules for all metal layers and implant layers as well as provides a "Bathtub" option for lower stack height, improving the sensors' angular response.
"By allowing significantly smaller pixels, higher resolution and enhanced pixel performance, our new platform ideally serves our customers' needs for the professional CIS markets, allowing them to create new business opportunities, expand the span of applications accessible for their designs, and enlarge their market share," said Jonathan Gendler, Director of CIS Marketing. "We have received enthusiastic feedback from all of our customers on the opportunity to keep working with our established process environment and reuse their design block IP, while being able to shrink the pixel array and die size. This new platform not only improves the cost model of their products, but at the same time enhances device performance."
The new hybrid CIS process platform will be offered for prototyping for select customers in Q3 2012, and for production towards the end of 2012. The new process and other advances will be showcased at the Image Sensors (IS) conference in London on March 20-22, 2012.
According to Yole Development, the forecast for high-end CMOS image sensors is expected to be ~$2B in 2015 with a CAGR of 13%.
