24.1 Evolution of Optical Structure in Image Sensors (Invited)
N. Teranishi, H. Watanabe, T. Ueda, N. Sengoku, Panasonic Corporation
Monolithic optical structures for light gathering in image sensors are focused. First, microlens progresses, such as gapless microlens, inner microlens and light pipe are explained. Then, back side illumination (BSI) is compared with front side illumination (FSI). Lastly, recent FSI technology, SmartFSI, is reported along with its pixel shrinkage results.
This presentation is supposed to explain how Panasonic claims on making small FSI pixel better than BSI.
24.2 Suppression of Crosstalk by Using Backside Deep Trench Isolation for 1.12µm Backside Illuminated CMOS Image Sensor
Y. Kitamura, H. Aikawa, K. Kakehi, T. Yosho, K. Eda, T. Minami, S. Uya, Y. Takegawa, H. Yamashita, Y. Kohyama, T. Asami, Toshiba Corporation
1.12um backside illuminated CMOS image sensor with backside deep trench isolation (DTI) has been demonstrated for the first time. DTI is fabricated on backside surface after wafer bonding and grinding process. Backside DTI makes its layout simple because no transistor isolation exists on backside. We have confirmed 50% reduction of crosstalk.
Many groups have experimented with DTI idea, but the higher dark current and hot pixel rate prevented its productization so far. I wonder whether Toshiba engineers were able to solve these problems.
24.3 How to Achieve Ultra High Photoconductive Gain for Transparent Oxide Semiconductor Image Sensors
S. Lee, A. Nathan*, J. Robertson*, University College London, *Cambridge University
This work presents a complete and quantitative analysis of the ultra-high extrinsic quantum efficiency in amorphous oxide hetero-TFT image sensors, taking into account the high sub-gap optical absorption due to oxygen vacancies, extended electron lifetime due to retarded recombination, and the reduced transit time associated with short channel lengths.
24.4 InGaAs/InP SPAD with Improved Structure for Sharp Timing Response
A. Tosi, F. Acerbi, M. Anti, F. Zappa, Politecnico di Milano
We designed and fabricated an In0.53Ga0.47As/InP Single-Photon Avalanche Diode with improved layer structure and diffusion geometry in order to achieve good detection efficiency (30% at 1550 nm), low afterpulsing (gate repetition frequency > 1 MHz) and good timing performance (timing response has 57 ps FWHM and 30 ps tail).
24.5 High Photocurrent and Quantum Efficiency of Graphene Stack Photodetector Assembled by Layer-by-Layer Transfer
H.-M. Li, T.-Z. Shen, D.-Y. Lee, W. J. Yoo, Sungkyunkwan University
A graphene stack (GS) structure assembled by layer-by-layer (LBL) transfer of single-layer graphene (SLG) is applied in field effect transistors (FETs) for photodetection. Excellent optoelectronic performance of ~3.6 times increased photocurrent (PC) together with increased internal/external quantum efficiency (IQE/EQE) is obtained in the LBL-GS-FET compared to the conventional SLG-FET, owing to (i) the improved electrical transport, e.g., carrier mobility (4.1 times higher), sheet resistance (61% reduced) and contact resistance (81% reduced) etc., and (ii) the increased optical absorption (over fivefold higher in the visible spectrum). A photovoltaic (PV) model of the LBL-GS-FET was established, indicating a peak of PC generation due to the optimized gate modulation. Both the experimental and theoretical results suggest the LBL-GS as an excellent material for high efficiency optoelectronics.
Session 12 too has a paper on solar energy harvesting image sensor:
12.2 Hybrid CIS/Si Near-IR Sensor and 16% PV Energy-Harvesting Technology
C.-H. Shen, J.-M. Shieh, T.-T. Wu, C.W. Liu, C. Hu, F.-L. Yang, National Nano Device Laboratories, *University of California, Berkeley
Hydrogen-plasma-enhanced Se vapor selenization is used to produce efficient Na-free CuInSe2 (CIS) sensor and solar cell, and low temperature plasma-deposited Si thin film solar cell and transistor with 400 cm2/V-s mobility are stacked on top the CIS layer. For the first time, we report a novel stacked Si/CIS/Si solar cell design that provides 15.8%-efficient bifacial operation. The Si TFT and back side Si solar cell is also an effective UV-visible band filter reducing light degradation and environmental noise on CIS image sensor. This hybrid image sensing and energy-harvesting technology is intended for applications in multi-functional panel with CIS performing both stacked solar cell and stacked TFT/sensor functions but in separate areas.
Session 33 on 3D stacking has a paper on 3D-integrated image processor:
33.2 Characterization of Chip-Level Hetero-Integration Technology for High-Speed, Highly Parallel 3D Stacked Image Processing System
K.-W. Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, J.-C. Bea, H. Hashimoto, T. Fukushima, T. Tanaka, M. Koyanagi, Tohoku University
We demonstrate the chip-level hetero-integration technology for high speed and highly parallel 3D stacked image processing system. The different function chips, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D stacked image processing system in chip-level. The fundamental functions of each layer are characterized in the prototype 3D stacked image processing system.
While not directly related to image sensors, Random Telegraph Noise (RTN) is starting to affect digital circuits in the new highly scaled technologies. Session 19 and 25 discuss it in a number of papers, such as this one:
25.6 Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty Under Low Voltage Operation
T. Matsumoto, K. Kobayashi*, H. Onodera, Kyoto University, *Kyoto Institute of Technology
By measuring 1680 ROs fabricated in a commercial 40 nm CMOS technology, statistical nature of RTN-induced delay fluctuation is described. Small number of samples have a large RTN-induced delay fluctuation. It is found that the impact of RTN-induced delay fluctuation becomes as much as 10.4% of nominal oscillation frequency under low supply voltage (0.65V) operation. It is also found that more than 50% reduction of frequency uncertainty can be achieved under 0.75V operation by slightly increasing the transistor size. The impact of the parameters that can be changed by circuit designer is clarified in view of RTN-induced CMOS logic delay uncertainty.
